The present invention relates to a method and/or architecture for phase acquisition in phase lock loops (PLLs) generally and, more particularly, to a method and/or architecture for acquisition when locking to a new frequency in a PLL.
In general, PLLs are considered clock multipliers. For example, an input clock of 10 Mhz can be multiplied by a PLL to yield an output frequency of 1000 Mhz. Ideally, the clock multiplication would result in an output clock that is in perfect phase alignment with the input clock.
Referring to FIG. 1, a conventional PLL architecture 10 is shown. The PLL 10 includes a phase frequency detector (PFD) 12, a filter 14, a voltage controlled oscillator (VCO) 16, and a divider 18. The PFD 12 sends the filter 14 information about the frequency and phase of the reference signal relative to the feedback clock. The filter 14 integrates the filter information into a voltage. The VCO 16 converts the voltage information into a frequency. The divider 18 divides down the higher speed frequency for a comparison by the PFD 12. A divider 20 divides an input frequency before being presented to the PFD 12.
Referring to FIG. 2, a frequency versus time graph 50 is shown. The graph 50 illustrates the lock time of the circuit 10. The graph 50 also illustrates the feedback (FB) frequency of the circuit 10.
One conventional approach, xe2x80x9cA 6-Ghz Integrated Phase-Locked Loop Using AlGaAs/GaAs Heterojuntion Bipolar Transistorxe2x80x9d, IEEE, Journal of Solid-State Circuits, vol. SC-27, pp. 1752-1762, December 1992, discloses fine and coarse control of the VCO. The PLL operates in high gain (Mhz/V) and low gain modes. The high gain mode will typically result in faster lock time while increasing jitter. Once the system is close to locking, the system switches to the lower VCO gain. The switch achieves fast lock time without sacrificing jitter. However, such an approach complicates VCO design. Specifically, additional parasitic effects are created due to the dual gain circuit. The approach also requires complete gain characterization for both non-linear gains.
Another conventional approach includes switching large resistor or small capacitor values in the filter. Such switching results in faster pulse integration from the PFD. However, switching resistors or capacitors of the filter is not preferred, since such switching transistors can interfere with the filter (i.e., the resistance of the pass gates).
Another conventional approach includes switching large currents in the filter. Such switching results in faster, frequency correction due to the large currents charging the filter components faster. However, current switching complicates filter/pump design (i.e., the pump needs to handle multiple levels of currents). Current switching pumps are difficult to implement, and particularly difficult if the pump implements common mode compensation. Furthermore, higher currents result in larger devices and higher parasitic effects. Additionally, such an approach slows the pump speed and increases noise coupling.
The present invention concerns an apparatus comprising a phase lock loop (PLL) and a lock circuit. The PLL may be configured to multiply an input frequency in response to a lock signal. The lock circuit may be configured to generate the lock signal. The PLL may also be configured to select a reference frequency as (i) the input frequency when in a first mode and (ii) a divided frequency of the input frequency when in a second mode.
The objects, features and advantages of the present invention include providing a method and/or architecture for fast acquisition when locking to a new frequency that may (i) provide simplicity in design, (ii) simplify design implementation methodology, (iii) achieve a faster lock using digital dividers, (iv) be implemented without changes to pre-existing analog blocks, (v) avoid pump headroom/speed issues, since multiple currents are not generally needed, (vi) have lower noise, which, may avoid complex filter design, (vii) be implemented without switching resistors or capacitors, (viii) avoid complex VCO design, (e.g., without multi-gain VCOs), (ix) be easily modified for faster/slower lock rates, and/or (x) enable fast lock/acquisition for simulation purposes.